Die level product modeling without die level input data
US11972987B2 · kind B2 · utility
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12Claims
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Key dates
| Filing date | Oct 16, 2020 |
| Grant date | Apr 30, 2024 |
| Priority date | — |
| Expiry date | Aug 10, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L22/14
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A machine learning model for each die for imputing process control parameters at the die. The model is based on wafer sort parametric measurements at multiple test sites across the entire wafer, as well as yield results for the wafer. This allows for a better analysis of outlier spatial patterns leading to improved yield results.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.