Differential analog multiplier-accumulator
US11977936B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 31, 2020 |
| Grant date | May 7, 2024 |
| Priority date | — |
| Expiry date | Jan 1, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2207/4824
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A differential multiplier-accumulator accepts A and B digital inputs and generates a dot product P by applying the bits of the A input and the bits of the B inputs to respective positive and negative unit elements comprised of groups of AND gates coupled to charge transfer lines through a capacitor Cu. Each positive and negative unit element receives one bit of the B input applied to all of the AND gates of the unit element, and each positive and negative unit element having the bits of A applied to each associated AND gate input of each unit element. The AND gates are coupled to charge transfer lines through a capacitor Cu, and the charge transfer lines couple to binary weighted charge summing capacitors and to an analog to digital converter to generate a digital output product. The charge transfer lines may span multiple unit elements.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.