Local reference voltage generator for non-volatile memory
US11978494B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 17, 2023 |
| Grant date | May 7, 2024 |
| Priority date | — |
| Expiry date | Feb 17, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/04
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of operating a memory device that includes the steps of receiving a read command and a target address in a non-volatile memory (NVM) array, in which the NVM array is divided into a plurality of blocks based on row and column addresses, performing a read operation on NVM cells in the target address and coupling an output of each NVM cell read to a sensing circuit, generating a local reference voltage based on a base reference voltage and an adjustment reference voltage corresponding to the target address of the NVM cells being read and a block that the NVM cells belong thereto, and offsetting the base reference voltage with the adjustment reference voltage, and coupling the local reference voltage to the sensing circuit. Other embodiments are also described.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.