Method of manufacturing semiconductor devices and semiconductor devices
US11978675B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 22, 2021 |
| Grant date | May 7, 2024 |
| Priority date | — |
| Expiry date | Feb 25, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/83
Abstract
A semiconductor device includes a gate structure disposed over a channel region, and a source/drain region. The gate structure includes a gate dielectric layer over the channel region, a first work function adjustment layer, over the gate dielectric layer, a first shield layer over the first work function adjustment layer, a first barrier layer, and a metal gate electrode layer. The first work function adjustment layer is made up of n-type work function adjustment layer and includes aluminum. The first shield layer is made of at least one selected from the group consisting of metal, metal nitride, metal carbide, silicide, a layer containing one or more of F, Ga, In, Zr, Mn and Sn, and an aluminum containing layer having a lower aluminum concentration than the first work function adjustment layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.