Substrate with cut semiconductor pieces having measurement test structures for semiconductor metrology
US11978679B2 · kind B2 · utility
0Cited by
12References
5Claims
0Family size
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Inventor
Key dates
| Filing date | May 3, 2021 |
| Grant date | May 7, 2024 |
| Priority date | — |
| Expiry date | Apr 16, 2042 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02P90/02
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A device used for semiconductor metrology includes a substrate and a plurality of pieces from one or more semiconductor wafers. Each piece of the plurality of pieces is bonded to the substrate at a respective position on the substrate. Each piece of the plurality of pieces includes a respective instance of a measurement test structure and an alignment mark. Each piece of the plurality of pieces has a known location from the one or more semiconductor wafers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.