Semiconductor package device
US11978696B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 4, 2022 |
| Grant date | May 7, 2024 |
| Priority date | — |
| Expiry date | Jul 3, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Disclosed is a semiconductor package device comprising a semiconductor chip including first and second chip pads on an active surface of the semiconductor chip, and a redistribution substrate on the first and second chip pads. The redistribution substrate includes first and second redistribution patterns sequentially stacked on the active surface. The first redistribution pattern includes a first via part and a first via pad part vertically overlapping the first via part. The second redistribution pattern includes a second via part and a second via pad part vertically overlapping the second via part. The first via part contacts the first chip pad. The second via part contacts the second chip pad. A length of the second via part is greater than that of the first via part.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.