Vertical etch heterolithic integrated circuit devices
US11978808B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 2, 2022 |
| Grant date | May 7, 2024 |
| Priority date | — |
| Expiry date | May 7, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2224/40137
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Vertical etch heterolithic integrated circuit devices are described. A method of manufacturing NIP diodes is described in one example. A P-type substrate is provided, and an intrinsic layer is formed on the P-type substrate. An oxide layer is formed on the intrinsic layer, and one or more openings are formed in the oxide layer. One or more N-type regions are implanted in the intrinsic layer through the openings in the oxide layer. The N-type regions form cathodes of the NIP diodes. A dielectric layer deposited over the oxide layer is selectively etched away with the oxide layer to expose certain ranges of the intrinsic layer to define a geometry of the NIP diodes. The intrinsic layer and the P-type substrate are vertically etched away within the ranges to expose sidewalls of the intrinsic layer and the P-type substrate. The P-type substrate forms the anodes of the NIP diodes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.