Methods and structures for semiconductor device testing
US11982709B2 · kind B2 · utility
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20Claims
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Key dates
| Filing date | May 20, 2022 |
| Grant date | May 14, 2024 |
| Priority date | — |
| Expiry date | Nov 11, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2223/54426
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
A structure for performing analysis includes a first opening formed on a back side of a substrate and passing through the substrate, a second opening connected with a bottom of the first opening and penetrating into a first dielectric layer formed on a front side of the substrate, a first conductive layer formed on a sidewall of the second opening and a contact element in the first dielectric layer, and a second conductive layer formed on a second dielectric layer. The first conductive layer contacts the second conductive layer electrically.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.