Reset and safe state logic generation in dual power flow devices
US11983025B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 17, 2022 |
| Grant date | May 14, 2024 |
| Priority date | — |
| Expiry date | Oct 17, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/3287
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An electric device includes: a first power domain; a second power domain; a third power domain, where during power-up, the third, the second, and the first power domains are configured to be powered up sequentially, where during standby-exit, the first, the second, and the third power domains are configured to be powered up sequentially; isolation paths that provide controlled signal transmission among the first, the second, and the third power domains, where each isolation path includes an isolation circuit between an input power domain and an output power domain of the isolation path; and a control circuit in the first power domain, where for each isolation path, the control circuit is configured to generate an isolation control signal for the isolation circuit, where the isolation circuit is configured enable or disable signal transmission along the isolation path.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.