Path margin monitor integration with integrated circuit
US11983032B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Apr 12, 2022 |
| Grant date | May 14, 2024 |
| Priority date | — |
| Expiry date | Nov 25, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/31726
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
The timing margin of various signal paths in an integrated circuit is monitored by components on the integrated circuit itself. Path margin monitor (PMM) circuits on the integrated circuit receive (a) functional signals propagating along signal paths in the integrated circuit, and (b) corresponding clock signals that are used to clock the functional signals. The PMM circuits output signals (PMM signals) which are indicative of the actual timing margins for the signal paths. For convenience, these will be referred to as path margins. A controller is also integrated on the integrated circuit. The controller controls the PMM circuits. It also receives and analyzes the PMM signals to monitor the path margins across the integrated circuit. Automated software is used to automatically insert instances of the PMM circuits into the design of the integrated circuit. The controller may also be automatically configured and inserted into the design.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.