Connecting random variables to coverage targets using an ensemble of static analysis, dynamic analysis and machine learning and guided constraint solving of the random variables during simulation of an integrated circuit
US11983474B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 23, 2021 |
| Grant date | May 14, 2024 |
| Priority date | — |
| Expiry date | Sep 1, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/3323
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for verifying an integrated circuit (IC) design described in a hardware description or hardware verification language (HDHVL) is provided. The method includes identifying connections between random variables and coverage areas of the IC design, as described in HDHVL code, the connections being identified by determining which coverage areas of the IC design will be influenced during simulation by which random variables. The method can further include storing the identified connections in a database, and using, by a processor, connections retrieved from the database to simulate and verify the coverage areas of the IC design.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.