Software-defined wafer-level switching system design method and apparatus
US11983481B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 12, 2023 |
| Grant date | May 14, 2024 |
| Priority date | — |
| Expiry date | Jul 12, 2043 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02P90/30
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present disclosure relates to software-defined methods and apparatuses for designing a wafer-level switching system, including: determining wafer-level switching system layout constraints; constructing a target wafer-level switching system and determining parameters, and designing a logical topology of a switching network; designing a layout of the switching chiplets on the wafer substrate; respectively designing interface structures of external chiplets and internal chiplets; configuring a switching mode and an enable state of each port of the switching chiplets; ending the process when the target logical topology can be achieved by the wafer-level switching system; otherwise, reconstructing a logical topology of a switching network and mapping it to the substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.