Multi-threaded processor with power granularity and thread granularity
US11983537B1 · kind B1 · utility
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19Claims
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Key dates
| Filing date | Dec 21, 2022 |
| Grant date | May 14, 2024 |
| Priority date | — |
| Expiry date | Dec 21, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3851
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A multi-stage processor has a pre-fetch stage, and a sequence of pipelined processor stages. A thread map register contains thread identifiers, and a thread map valid register has locations corresponding to the thread map register and indicating whether a value in the thread map register is to be fetched or not, and a thread map length register indicates the number of thread map register locations forming a canonical sequence of thread identifiers to the pre-fetch stage. The pre-fetch stage does not act on a thread identifier with a not valid thread map valid value, thereby saving power in low demand conditions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.