Plurality of stacked transistors attached by solder balls
US11984387B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Mar 3, 2022 |
| Grant date | May 14, 2024 |
| Priority date | — |
| Expiry date | Nov 8, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/471
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A first chip includes a first surface, a second surface, a first semiconductor layer including a nitride semiconductor layer, a first electrode pad located at the first surface, a second electrode pad located at the first surface, a first gate pad located at the first surface, and a third electrode pad located at the first surface. A second chip is located on the first surface of the first chip. The second chip includes a third surface facing the first surface of the first chip, a fourth surface, a second semiconductor layer including a channel of a second conductivity type, a fourth electrode pad located at the fourth surface, a fifth electrode pad located at the third surface and bonded to the second electrode pad of the first chip, and a second gate pad located at the third surface and bonded to the third electrode pad of the first chip.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.