Low power inverter-based CTLE
US11984817B2 · kind B2 · utility
0Cited by
4References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 10, 2020 |
| Grant date | May 14, 2024 |
| Priority date | — |
| Expiry date | Nov 27, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH02M7/4835
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
An example continuous time linear equalizer (CTLE) includes a first inverter; a second inverter having an input to receive an input signal; a capacitor coupled between an input of the first inverter and the input of the second inverter; a resistor coupled between a common-mode voltage and the input of the first inverter; a third inverter having an output to provide an output signal; and a node comprising an output of the first inverter, an output of the second inverter, an input of the third inverter, and the output of the third inverter.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.