PIM cancellation architecture
US11984919B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 3, 2022 |
| Grant date | May 14, 2024 |
| Priority date | — |
| Expiry date | Oct 3, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L27/01
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
Embodiments herein describe a PIM correction circuit. In a base station, TX and RX RF changes, band pass filters, duplexers, and diplexers can have severe memory effects due to their sharp transition bandwidth from pass band to stop band. PIM interference, generated by the TX signals and reflected onto the RX RF chain will include these memory effects. These memory effects make PIM cancellation complex, requiring complicated computations and circuits. However, the embodiments herein use a PIM correction circuit that separates the memory effects of the TX and RX paths from the memory effects of PIM, thereby reducing PIM cancellation complexity and hardware implementation cost.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.