Method for manufacturing memory and same

US11985815B2 · kind B2 · utility

Assignee

• CHANGXIN MEMORY TECHNOLOGIES, INC. · CN

Inventors

• Er-Xuan Ping · Boise, US
• Zhen Zhou · Emeryville, US
• Lingguo Zhang · Hefei, CN

Key dates

• Filing date: Sep 20, 2021
• Grant date: May 14, 2024
• Expiry date: Jan 24, 2042

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10B12/485

Abstract

A method for manufacturing a memory includes the following operations. A substrate and a plurality of separate initial bit line contact structures are provided, in which a plurality of active regions are formed in the substrate, and each of the initial bit line contact structures is electrically connected with the active regions, and each of the initial bit line contact structures is partially located in the substrate. Pseudo-bit line structures on the tops of the initial bit line contact structures are formed. The initial bit line contact structures are etched to form bit line contact layers and gaps between the substrate and the side walls of the bit line contact layers. First dielectric layers are formed on the side walls of the pseudo-bit line structures, in which the first dielectric layers are also located right above the gaps.