Three-dimensional memory devices having dummy channel structures and methods for forming the same
US11985824B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 29, 2020 |
| Grant date | May 14, 2024 |
| Priority date | — |
| Expiry date | Dec 23, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/02255
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Three-dimensional (3D) memory devices and methods for forming the 3D memory devices are provided. In one example, a 3D memory device includes a substrate and a memory stack including interleaved conductive layers and dielectric layers on the substrate. The memory stack includes a core structure and a staircase structure. The staircase structure is on one side of the memory stack. The 3D memory device also includes a dummy channel structure extending vertically through the staircase structure. The dummy channel structure includes a plurality of sections along a vertical side of the dummy channel structure. The plurality of sections respectively interface with the interleaved conductive layers in the staircase structure. At least one of the plurality of sections includes a non-flat surface at an interface between the at least one of the plurality of sections and a corresponding conductive layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.