Semiconductor arrangement and method for producing a semiconductor arrangement
US11990405B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 25, 2022 |
| Grant date | May 21, 2024 |
| Priority date | — |
| Expiry date | Jul 14, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2225/06593
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for producing a semiconductor arrangement includes applying a metallization layer on an upper main side of a lower semiconductor chip, structuring the metallization layer, and fastening an upper semiconductor chip on the upper main side of the lower semiconductor chip by a bonding material, wherein the metallization layer is structured such that the metallization layer has an increased roughness along a contour of the upper semiconductor chip in comparison with the rest of the metallization layer, wherein wetting of the upper main side of the lower semiconductor chip by the bonding material is limited by a structure in the metallization layer to a region below the upper semiconductor chip.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.