Semiconductor package
US11990452B2 · kind B2 · utility
0Cited by
9References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 13, 2023 |
| Grant date | May 21, 2024 |
| Priority date | — |
| Expiry date | Mar 13, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/18161
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor package includes a first semiconductor chip comprising a semiconductor substrate and a redistribution pattern on a top surface of the semiconductor substrate, the redistribution pattern having a hole exposing an inner sidewall of the redistribution pattern, a second semiconductor chip on a top surface of the first semiconductor chip, and a bump structure disposed between the first semiconductor chip and the second semiconductor chip. The bump structure is disposed in the hole and is in contact with the inner sidewall of the redistribution pattern.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.