Three-dimensional memory devices having isolation structure for source select gate line and methods for forming the same
US11990506B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 29, 2020 |
| Grant date | May 21, 2024 |
| Priority date | — |
| Expiry date | Jan 1, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B43/35
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Embodiments of three-dimensional (3D) memory devices and methods for forming the same are disclosed. In an example, a 3D memory device includes a substrate, a memory stack on the substrate, a plurality of channel structures each extending vertically through the memory stack, and one or more isolation structures. The memory stack includes a plurality of interleaved conductive layers and dielectric layers. An outmost one of the conductive layers toward the substrate is a source select gate line (SSG). Each isolation structure surrounds at least one of the channel structures in a plan view to separate the SSG and the at least one channel structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.