Memory device and method for fabricating the same
US11991930B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 9, 2022 |
| Grant date | May 21, 2024 |
| Priority date | — |
| Expiry date | Nov 9, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N50/80
Abstract
A structure includes a substrate, a transistor, a contact, an oxygen-free etch stop layer, an oxygen-containing etch stop layer, a dielectric layer, and a via. The transistor is on the substrate. The contact is on a source/drain region of the transistor. The oxygen-free etch stop layer spans the contact. The oxygen-containing etch stop layer extends along a top surface of the oxygen-free etch stop layer. The dielectric layer is over the oxygen-containing etch stop layer. The via passes through the dielectric layer, the oxygen-containing etch stop layer, and the oxygen-free etch stop layer and lands on the contact. The memory stack lands on the via.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.