Raw bit error rate based trim level adjustments for memory
US11994942B2 · kind B2 · utility
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4References
18Claims
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Key dates
| Filing date | Dec 21, 2021 |
| Grant date | May 28, 2024 |
| Priority date | — |
| Expiry date | Apr 23, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/0409
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processing device coupled to the memory device can be configured to monitor respective raw bit error rates (RBERs) corresponding to a plurality of groups of memory cells of the memory device. The processing device can also be configured to responsive to determining that an RBER corresponding to a particular group of the plurality of groups of memory cells has met a criteria, adjust a read window budget corresponding to the particular group of memory cells.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.