Single-level cell block storing data for migration to multiple multi-level cell blocks
US11995328B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 18, 2022 |
| Grant date | May 28, 2024 |
| Priority date | — |
| Expiry date | Aug 18, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/7201
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Implementations described herein relate to memory devices including a single-level cell (SLC) block storing data for migration to multiple multi-level cell (MLC) blocks. In some implementations, a memory device includes multiple MLC blocks that include MLCs, with each MLC being capable of storing at least four bits of data, and multiple SLC blocks that can store data prior to the data being written to one of the MLC blocks. Each SLC block may be capable of storing different data sets that are destined for storage in different MLC blocks. The memory device may include a mapping component that can store a mapping table that includes multiple entries, in which an entry indicates a mapping between a memory location in the SLC blocks and a corresponding MLC block for which data stored in the memory location is destined. Numerous other implementations are described.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.