Plane balancing in a memory system
US11995345B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 13, 2022 |
| Grant date | May 28, 2024 |
| Priority date | — |
| Expiry date | Aug 15, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F3/0679
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods, systems, and devices for plane balancing in a memory system are described. A memory system may select a memory die for writing a set of data. The memory die may include a plurality of planes each of which may include a respective plurality of blocks of memory cells. Based on selecting the memory die, the memory system may determine a first plane of the plurality of planes that has a first quantity of blocks with an availability status and a second plane of the plurality of planes that has a second quantity of blocks with the availability status. The memory system may write the set of data to the plurality of planes, excluding at least the first plane, based at least in part on the first quantity of blocks and the second quantity of blocks.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.