Storing parity during refresh operations
US11995353B2 · kind B2 · utility
0Cited by
1References
24Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 18, 2022 |
| Grant date | May 28, 2024 |
| Priority date | — |
| Expiry date | Aug 5, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F3/0679
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods, systems, and devices for storing parity during refresh operations are described. In some examples, refresh operations may be performed on a memory device when the memory device is idle. For example, a refresh operation may entail performing a logical operation on first data and a first set of parity bits and second data and a second set of parity bits. The logical operation may generate a third set of parity bits which may be used for data retention purposes. Moreover, during a read operation, the third set of parity bits may be used to recover corrupt or otherwise invalid data in the event of an error.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.