Method for forming lead wires in hybrid-bonded semiconductor devices
US11996322B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 3, 2022 |
| Grant date | May 28, 2024 |
| Priority date | — |
| Expiry date | May 3, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/31116
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Embodiments of a hybrid-bonded semiconductor structure are disclosed. The semiconductor structure comprises a first conductive structure and a second conductive structure in a base dielectric layer. The base dielectric layer has a non-flat top surface. A first top surface of the first conductive structure is non-coplanar with a second top surface of the second conductive structure. The semiconductor structure further comprises an alternating dielectric layer stack comprising a plurality of dielectric layers sequentially disposed on the base dielectric layer, wherein at least two of the plurality of dielectric layers have non-uniform thickness. The semiconductor structure further comprises a first lead wire and a second lead wire formed in the alternating dielectric layer stack and electrically connected to the first conductive structure and the second conductive structure, respectively.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.