Controlling a processor clock
US12001263B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 5, 2023 |
| Grant date | Jun 4, 2024 |
| Priority date | — |
| Expiry date | Apr 5, 2043 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
There is disclosed a method of controlling the frequency of a clock signal in a processor. The method selects a first clock generator to provide a processor clock signal for executing an application. If a threshold event is detected, a second clock generator is selected. The method reduces the frequency of a clock signal generated by the first clock generator while a processor clock signal is being provided for execution of an application from the second clock generator. The second clock generator generates a clock at a lower speed than the first clock generator. After a predetermined time, the first clock generator is reselected to provide the processor clock signal. The threshold detection is repeated until an optimum clock frequency is discovered.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.