Device and method for reducing save-restore latency using address linearization

US12001265B2 · kind B2 · utility

Assignee

• Advanced Micro Devices, Inc. · US

Inventors

• Benjamin Tsien · Fremont, US
• Alexander J. Branover · East Sharon, US
• Christopher T. Weaver · Cupertino, US
• Indrani Paul · Round Rock, US
• Mihir Shaileshbhai Doctor · Sunnyvale, US
• John P. Petry · Newton, US
• Stephen V. Kosonocky · Fort Collins, US
• Thomas J. Gibney · Boxborough, US
• Jose G. Cruz · Boxborough, US
• Pravesh Gupta · Bengaluru, IN
• Chintan S. Patel · Austin, US

Key dates

• Filing date: Sep 23, 2021
• Grant date: Jun 4, 2024
• Expiry date: Dec 11, 2041

Classification

• Technology area (CPC Y): Emerging Cross-Sectional Technologies
• CPC primary: Y02D10/00
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

Devices and methods for transitioning between power states of a device are provided. A program is executed using data stored in configuration registers assigned to a component of a device. For a first reduced power state, data of a first portion of the configuration registers is saved to the memory using a first set of linear address space. For a second reduced power state, data of a second portion of the configuration registers is saved to the memory using a second set of linear address space and data of a third portion of the configuration registers is saved to the memory using a third set of linear address space.