Patent · US Active

Vector fetch bus error handling

US12001270B2 · kind B2 · utility

0Cited by

0References

17Claims

0Family size

Assignee

MICROCHIP TECHNOLOGY INCORPORATED · US

Inventors

Michael Catherwood · Georgetown, US
David Mickey · Chandler, US

Key dates

Filing date	Dec 6, 2022
Grant date	Jun 4, 2024
Priority date	—
Expiry date	Jan 11, 2043

Classification

Technology area (CPC G)Physics
CPC primaryG06F11/0793
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A computer system includes a non-transitory computer-readable memory to store (a) a vector table including an exception vector pointing to an exception handler and (b) a vector fail address of a vector fetch bus error handler, and a processor to identify an exception, initiate an exception vector fetch in response to the identified exception to read the exception vector from the vector table, identify a vector fetch bus error associated with the exception vector fetch, access the vector fail address of the vector fetch bus error handler in response to the vector fetch bus error, and execute the vector fetch bus error handler.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.