Semiconductor devices and electronic systems including the same
US12002511B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 22, 2021 |
| Grant date | Jun 4, 2024 |
| Priority date | — |
| Expiry date | Jul 21, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B43/40
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Semiconductor devices may include a peripheral circuit structure including circuits, a substrate on the peripheral circuit structure, a pair of word line cut structures extending in a first direction on the substrate, and a memory cell block between the pair of word line cut structures and on the substrate. The memory cell block may include a memory stack structure including gate lines overlapping each other in a vertical direction, an interlayer insulation layer on an edge portion of each of the gate lines, a dam structure extending through the gate lines and the interlayer insulation layer, an intersection direction cut structure extending through the memory stack structure and the interlayer insulation layer in the vertical direction and being spaced apart from the dam structure, and a dummy channel structures between the intersection direction cut structure and the dam structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.