Gate spacing in integrated circuit structures
US12002678B2 · kind B2 · utility
0Cited by
1References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 25, 2020 |
| Grant date | Jun 4, 2024 |
| Priority date | — |
| Expiry date | Aug 9, 2042 |
Classification
- Technology area (CPC B)Performing Operations; Transporting
- CPC primaryB82Y10/00
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Discussed herein is gate spacing in integrated circuit (IC) structures, as well as related methods and components. For example, in some embodiments, an IC structure may include: a first gate metal having a longitudinal axis; a second gate metal, wherein the longitudinal axis of the first gate metal is aligned with a longitudinal axis of the second gate metal; a first gate contact above the first gate metal; a second gate contact above the second gate metal; and an unordered region having an unordered lamellar pattern, wherein the unordered region is coplanar with the first gate contact and the second gate contact.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.