Hybrid pocket post and tailored via dielectric for 3D-integrated electrical device
US12002773B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 3, 2021 |
| Grant date | Jun 4, 2024 |
| Priority date | — |
| Expiry date | May 18, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10F77/20
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An electrical device includes a substrate, an insulating layer supported by the substrate, and an electrically conductive vertical interconnect disposed in a via hole of the insulating layer. The insulating layer may be configured to provide a coefficient of thermal expansion (CTE) that is equal to or greater than a CTE of the vertical interconnect to thereby impart axial compressive forces at opposite ends of the interconnect. The vertical interconnect may be a hybrid interconnect structure including a low CTE conductor post having a pocket that contains a high CTE conductor contact. At low operating temperatures, the high CTE conductor contact is under tension due to the higher CTE, and thus the high CTE conductor contact relieves strain in the device by void expansion and elongation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.