Gate-all-around integrated circuit structures having depopulated channel structures using bottom-up approach

US12002810B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Dax M. Crum · Beaverton, US
• Biswajeet Guha · Hillsboro, US
• Leonard P. GULER · Hillsboro, US
• Tahir Ghani · Portland, US

Key dates

• Filing date: Sep 28, 2018
• Grant date: Jun 4, 2024
• Expiry date: Aug 3, 2041

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/0128
• WIPO field: Micro-structural and nano-technology
• WIPO sector: Chemistry

Abstract

Gate-all-around integrated circuit structures having depopulated channel structures, and methods of fabricating gate-all-around integrated circuit structures having depopulated channel structures using a bottom-up approach, are described. For example, integrated circuit structure includes a first vertical arrangement of nanowires and a second vertical arrangement of nanowires above a substrate. The first vertical arrangement of nanowires has a greater number of nanowires than the second vertical arrangement of nanowires. The first vertical arrangement of nanowires has an uppermost nanowire co-planar with an uppermost nanowire of the second vertical arrangement of nanowires. The first vertical arrangement of nanowires has a bottommost nanowire below a bottommost nanowire of the second vertical arrangement of nanowires. A first gate stack is over the first vertical arrangement of nanowires. A second gate stack is over the second vertical arrangement of nanowires.