Analog memory-based complex multiply-accumulate (MACC) compute engine
US12003240B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 31, 2022 |
| Grant date | Jun 4, 2024 |
| Priority date | — |
| Expiry date | Oct 31, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2207/4814
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A circuit comprises a first pulse-width modulator configured to generate a first pulse based on a first input, a second pulse-width modulator configured to generate a second pulse based on a second input, a first differential circuit comprising a first transistor, a second transistor, a first resistor, and a second resistor, and a second differential circuit comprising a first transistor, a second transistor, a first resistor, and a second resistor. A gate of the first transistor of the first differential circuit and a gate of the second transistor of the first differential circuit, and a gate of the first transistor of the second differential circuit and a gate of the second transistor of the second differential circuit are configured to be controlled by the first and second pulse width modulators based on the first input and the second input.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.