Process for laminating graphene-coated printed circuit boards
US12004308B2 · kind B2 · utility
0Cited by
16References
34Claims
0Family size
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Key dates
| Filing date | Jul 1, 2021 |
| Grant date | Jun 4, 2024 |
| Priority date | — |
| Expiry date | May 3, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K2203/1338
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
Processes for laminating a graphene-coated printed circuit board (PCB) are disclosed. An example laminated PCB may include a lamination stack that may include an inner core, an adhesive layer, and at least one graphene-metal structure. Pressure and heat—which may be applied under vacuum or controlled gas atmosphere—may be applied to the lamination stack, after all materials have been placed. The graphene of the graphene-metal structure is designed to promote high frequency performance and heat management within the PCB.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.