Apparatus and method for managing power of test circuits
US12007429B2 · kind B2 · utility
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Key dates
| Filing date | Jun 24, 2022 |
| Grant date | Jun 11, 2024 |
| Priority date | — |
| Expiry date | Jun 24, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/31721
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
An apparatus has a semiconductor wafer hosting rows and columns of chips, where the rows and columns of chips are separated by scribe lines. Voltage regulators are positioned within the scribe lines. Each voltage regulator is connected to one or more chips. Selection circuitry is positioned within the scribe lines. The selection circuitry governs access to a chip being tested.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.