On-chip interconnect for memory channel controllers
US12007913B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 29, 2022 |
| Grant date | Jun 11, 2024 |
| Priority date | — |
| Expiry date | Mar 29, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/8061
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods, systems, and apparatus, including computer-readable media, are described for an integrated circuit that accelerates machine-learning computations. The circuit includes processor cores that each include: multiple channel controllers; an interface controller for coupling each channel controller to any memory channel of a system memory; and a fetch unit in each channel controller. Each fetch is configured to: receive channel data that encodes addressing information; obtain, based on the addressing information, data from any memory channel of the system memory using the interface controller; and write the obtained data to a vector memory of the processor core via the corresponding channel controller that includes the respective fetch unit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.