Interconnect-based resource allocation for reconfigurable processors
US12008417B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 16, 2021 |
| Grant date | Jun 11, 2024 |
| Priority date | — |
| Expiry date | Apr 7, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L45/745
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The technology disclosed relates to interconnect-based resource allocation for reconfigurable processors. In particular, the technology disclosed relates to a runtime logic that is configured to receive target interconnect bandwidth and target interconnect latency, and rated interconnect bandwidth and rated interconnect latency. The runtime logic is further configured to respond by allocating, to configuration files defining an application graph, processing elements in a plurality of processing elements, and interconnects between the processing elements, and executing the configuration files using the allocated processing elements and the allocated interconnects.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.