Fabricating wafers with electrical contacts on a surface parallel to an active surface
US12009352B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 16, 2020 |
| Grant date | Jun 11, 2024 |
| Priority date | — |
| Expiry date | Mar 15, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2224/97
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
Provided herein include various examples of a method for manufacturing aspects of an apparatus, a sensor system. The method may include obtaining a first carrier bonded to an upper surface of the silicon wafer. This wafer includes through silicon vias (TSVs) extended through openings in a passivation stack, with electrical contacts coupled to portions of the TSVs exposed through these openings. The method may include de-bonding the first carrier from the upper surface of the silicon wafer. The method may include dicing the silicon wafer into subsections comprising dies.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.