Semiconductor device
US12009359B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 18, 2021 |
| Grant date | Jun 11, 2024 |
| Priority date | — |
| Expiry date | Jun 20, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/60
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor having transistors arranged side by side in one direction over a surface of a substrate and are connected in parallel. At least one passive element is disposed on at least one of regions between two adjacent ones of the transistors. The transistors each include a collector layer over the substrate, a base layer on the collector layer, and an emitter layer on the base layer. Collector electrodes are arranged in such a manner that each of the collector electrodes is located between the substrate and the collector layer of the corresponding one of the transistors and is electrically connected to the collector layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.