Systems and methods of decoding error correction code of a memory device with dynamic bit error estimation
US12009840B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 5, 2022 |
| Grant date | Jun 11, 2024 |
| Priority date | — |
| Expiry date | Jan 5, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/43
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A method, of decoding error correction code of a memory device with dynamic bit error estimation, can include generating at least one metric corresponding to one or more syndromes associated with a code word, the code word comprising an error correction code of a memory device, decoding the code word by a first decoder integrated with the memory device, in response to a determination that the metric satisfies a threshold associated with the syndromes, the first decoder having a first execution property, and decoding the code word by a second decoder integrated with the memory device, in response to a determination that the metric does not satisfy the threshold associated with the syndromes, the second decoder having a second execution property distinct from the first execution property, or in response to a determination that the metric satisfies the threshold associated with the syndromes, and in response to a determination to perform further decoding.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.