Method and device for monitoring gate signal of power semiconductor
US12013428B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 16, 2020 |
| Grant date | Jun 18, 2024 |
| Priority date | — |
| Expiry date | Dec 8, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K17/567
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
The present invention concerns a method and device for monitoring the gate signal of a power semiconductor (SI), the gate signal of the power semiconductor (SI) being provided by a gate driver (12), generates an expected signal (VGexp) that corresponds to the signal outputted by the gate driver (12) when no deterioration of the gate driver (12) and/or of the power semiconductor (SI) and/or of a load linked to the power semiconductor (SI) exists, compares the expected signal (VGexp) and the signal (VGmeas) outputted by the gate driver (12), determines if a deterioration of the gate driver (12) and/or of the power semiconductor (SI) and/or of a load linked to the power semiconductor (SI) exists using the result of the comparing of the expected signal (VGexp) and the signal (VGmeas) outputted by the gate driver (12).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.