Scaleable analog multiplier-accumulator with shared result bus
US12014151B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 31, 2020 |
| Grant date | Jun 18, 2024 |
| Priority date | — |
| Expiry date | Aug 30, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2207/4824
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A plurality of unit elements share a charge transfer bus, each unit element accepts A and B digital inputs and generates a product P as an analog charge transferred to the charge transfer bus, each unit element comprised of groups of AND gates coupled to charge transfer lines through a capacitor Cu. Each unit element receives one bit of the B input applied to all of the AND gates of the unit element, and each unit element having the bits of A applied to each associated AND gate input of each unit element. The AND gates of each unit element are coupled to charge transfer lines through a capacitor Cu, and the charge transfer lines couple to binary weighted charge summing capacitors which sum and scale the charges contributed by all unit elements to the charge transfer lines according to a bit weight and converted to a digital value output.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.