Multiplier-accumulator unit element with binary weighted charge transfer capacitors
US12014152B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 31, 2021 |
| Grant date | Jun 18, 2024 |
| Priority date | — |
| Expiry date | Jan 16, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M3/04
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A Unit Element (UE) has a digital X input and a digital W input, and comprises groups of NAND gates generating complementary outputs which are coupled to a differential charge transfer bus comprising a positive charge transfer line and a negative charge transfer line. The number of bits in the X input determines the number of NAND gates in a NAND-group and the number of bits in the W input determines the number of NAND groups. Each NAND-group receives one bit of the W input applied to all of the NAND gates of the NAND-group, and each unit element having the bits of X applied to each associated NAND gate input of each unit element. The NAND gate outputs are coupled through binary weighted charge transfer capacitors to a positive charge transfer line and negative charge transfer line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.