Semiconductor package and semiconductor module including the same
US12015015B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 10, 2023 |
| Grant date | Jun 18, 2024 |
| Priority date | — |
| Expiry date | Feb 10, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K1/181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor package includes a substrate including a first bonding pad and a first conductive pattern positioned at the same level and in contact with the first bonding pad; a lower semiconductor chip and an upper semiconductor chip stacked over the substrate, the lower and upper semiconductor chips respectively including a first lower chip pad and a first upper chip pad; a first lower bonding wire with first and second ends respectively connected to the first bonding pad and the first lower chip pad; and a first upper bonding wire with a first end connected to the first bonding pad and a second end connected to the first upper chip pad, the first end of the first upper bonding wire is located farther from the lower and upper semiconductor chips and closer to the first conductive pattern than the first end of the first lower bonding wire.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.