Transistor with single termination trench having depth more than 10 microns

US12015079B2 · kind B2 · utility

Assignee

• Polar Semiconductor, LLC · US

Inventors

• Noel Hoilien · Minneapolis, US
• Peter West · Gainesville, US
• Rajesh Appat · Eagan, US

Key dates

• Filing date: Aug 30, 2021
• Grant date: Jun 18, 2024
• Expiry date: Nov 23, 2041

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D64/111

Abstract

In one aspect, a method of fabricating a transistor includes depositing a first epitaxial layer; depositing a second epitaxial layer on the first epitaxial layer; forming a single termination trench in the second epitaxial layer; and filling the termination trench with a dielectric. A depth of the termination trench is greater than 10 microns. In another aspect, a transistor includes a first epitaxial layer; a second epitaxial layer on the first epitaxial layer; and a single termination trench in the second epitaxial layer. The termination trench is greater than 10 microns and is filled with a dielectric.