Using time-to-digital converters to delay signals with high accuracy and large range
US12019406B2 · kind B2 · utility
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18Claims
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Key dates
| Filing date | Nov 18, 2022 |
| Grant date | Jun 25, 2024 |
| Priority date | — |
| Expiry date | Nov 18, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/093
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A system delays input clock signals using time-to-digital converters (TDCs) to convert edges or the clock signals to digital values and storing the digital values in a memory. The digital values are retrieved from the memory based on a desired delay. A time counter used by the TDCs to determine the edges is also used determine the delay. The accuracy and range of the delay depends on the time counter and size of the memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.