Digital system synchronization
US12019464B2 · kind B2 · utility
0Cited by
3References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 15, 2021 |
| Grant date | Jun 25, 2024 |
| Priority date | — |
| Expiry date | Apr 16, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/18161
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A semiconductor package includes source clock circuitry to generate a source clock signal. Reference clock circuitry generates a reference clock signal. A first timing circuit includes a first source clock input to receive the source clock signal. First fan-out circuitry distributes the received source clock signal as a first distributed clock signal to a first set of clocked devices. A first delay circuit delays the received source clock signal by a first delay value based on a first phase difference between the first distributed clock signal and the reference clock signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.