Memory sub-system cache extension to page buffers of a memory array
US12019543B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 18, 2022 |
| Grant date | Jun 25, 2024 |
| Priority date | — |
| Expiry date | Aug 18, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/7203
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system includes a memory device having an array of memory cells coupled with a plurality of page buffers. At least a portion of the array is configured as single-level cell memory. A processing device is coupled to the memory device and includes cache, the processing device to perform operations including: detecting demand for the cache during a memory operation requiring access to the single-level cell memory; and causing metadata associated with the memory operation to be stored in one or more page buffers of the plurality of page buffers, the one or more page buffers operating as an extension of the cache available to the processing device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.